Field of the Invention
The present invention relates to a method for accessing a signal value of an FPGA at runtime. Likewise, the invention relates to a data processing device with a processor unit and an FPGA, whereby the data processing device is configured to carry out the above method. The invention also relates to a computer program product with computer-implemented instructions, said product which after loading and execution in a suitable data processing device performs the steps of the above method, and a digital storage medium with electronically readable control signals, which can interact with a programmable data processing device, so that the above method is executed. Finally, the present invention comprises a method for making an FPGA build based on an FPGA model using a hardware description language.
Description of the Background Art
The real-time simulation of complex, dynamic models because of the narrow time constraints imposes high demands on modern computation nodes. In automotive hardware-in-the-loop simulations (HiL), such models are used primarily where rapid control loops must be closed. This is the case, for instance, in the simulation of in-cylinder pressure sensors, which play an increasingly greater role in fuel consumption or exhaust gas reduction. But in controlled systems as well which have high dynamics, such as, for example, in electric motors, short cycle times and low latencies are indispensable. These can hardly be implemented any longer with CPU-based simulations.
Field programmable gate arrays (FPGAs) can support computation nodes during real-time simulation in that they take over the calculation of dynamic parts of a model. High real-time requirements can be easily met by using FPGAs because of the high flexibility and the possibility of parallel processing of signals. The FPGAs can be used as hardware accelerators for the CPUs of computation nodes. The DS5203-FPGA board from dSPACE, for example, represents such an enhancement for a HiL simulator. Accordingly, e.g., very dynamic parts of the environmental model are outsourced to the FPGA, so that sufficiently precise and rapid reaction times are preserved for the control device. An FPGA hardware configuration is typically generated based on an FPGA model using a hardware description language in a build process.
The models of a control system have become increasingly more complex because of more stringent requirements for accuracy and therefore also difficult to manage. In the automotive HiL environment, such models are created as a rule with the MATLAB/Simulink toolset from The MathWorks Inc. Simulink offers a block-based view of such models in the form of a block diagram. In a block diagram model, parts can be combined into subsystems and linked together with signals. The data flow between these blocks is shown by signal lines.
In a CPU-based real-time simulation, the block diagram of a model is first converted into C/C++ source files with the aid of the Simulink coder. These are then converted using a compiler into an executable application, which can be executed on a computation node with a real-time-capable operating system. In addition, in the case of the CPU build a trace file is generated which is a topology file with its graphical modeling, for example, in Simulink.
The conversion of a model into a CPU application has the result that the calculations of the simulation are performed sequentially in a fixed step size. A consistent image of all model states or model variables, such as, for example, data in the signal lines or input/output values of the blocks, is therefore always present in the main memory of the computation node. Due to the direct access to the main memory, the model variables can be analyzed and/or manipulated using an experimentation tool such as, for example, ControlDesk. Random read/write access to variables of the HiL simulation is possible. By using the trace files, signal values such as, e.g., motor rotation speed can be selected and output or manipulated by a display. In the HiL environment, these processes are grouped under the term “measuring” and “calibrating.”
An FPGA-based simulation can be modeled in a block diagram with Simulink with the aid of the Xilinx System Generator (XSG) and the FPGA Programming Blockset from dSPACE, similar to a CPU-based simulation.
In contrast to the CPU simulation, this model however is not converted into an iterative program language but into a hardware description language, which describes a customer-specific digital circuit. The description of the customer-specific circuit is converted by a synthesis process into an FPGA configuration data stream.
For debug purposes it is possible for some FPGAs to freeze and read the complete state of the FPGA. Because of the closed input/output behavior of the FPGA, it is not possible, however, in analogy to the main memory of a computation node to access any model states and to change these if necessary. Each model variable, which the user would like to measure or calibrate, must be provided by explicit modeling via signal lines to the interfaces of the FPGA. After this adjustment, the model must be converted again, which can take several hours. This circumstance can lead to very long development cycles of FPGA-based real-time simulations.